Hi All, Could anyone please tell me if I can check the count of L1 cache miss at runtime, say after x cycles? The cache profiler has the record of all the cache misses but is there any way I can get the information from it at runtime and pass it to its router/NI?
Also, I wanted to know if the data request packets which encounter a L1 cache miss travel through the Garnet interconnection network to reach to the L2 cache/memory or are they passed through the sequencer? I am a bit confused here. Can anyone please guide me? -- Thanks and Regards, Tejasi
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
