Hello All,
Does the classic memory model do any sort of address hashing or other
similar magic when storing data in the L1D cache?
I've been running a very simple microbenchmark with varying sizes of the
L1D cache and data set (in SE mode). For a very small number of
combinations of data set and cache size, miss rate goes through the roof
(>50x what might be expected based on other simulations). This is
consistent with e.g. a collision in a hash function for mapping logical
addresses to physical ones.
I thought I'd ask if this is expected behavior before I go digging
through the code.
Thanks,
Erik
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