Hello,
in my simulation I am having 3 cores- an atomic one used for the fast
forwarding and other 2 used for the main simulation.
I want to be able to change my workload from one core to another. How to do
that?
I have done the following.
Run the fast-fwd and then switchCpus from atomic to cpuA.
Lets say my workload has 3 intervals, I want in the last one to run on the cpuB.
I have implemented my own switchWorkloadCpu function which does exactly what
the switchCpus() does, except it calls takeWorkloadOverFrom instead
takeOverFrom.
The implementation of takeWorkLoadOverFrom is identical to that of
takeOverFrom, but I haven't included the binding and the un-binding of the
caches since I want these two cores to have separate caches.
So, the workload runs successfully on the cpuA for interval 1,2 and in the last
one it should run on the cpuB. However, there are 4 commited instructions on
the cpuA and none oon the cpuB and my simulation stops with the fatal error
simulare() limit reached.
What to do?
here is my takeWorkloadOverFrom:
BaseCPU::takeWorkloadOverFrom(BaseCPU *oldCPU)
{
assert(threadContexts.size() == oldCPU->threadContexts.size());
assert(_cpuId == oldCPU->cpuId());
assert(_switchedOut);
assert(oldCPU != this);
_pid = oldCPU->getPid();
_taskId = oldCPU->taskId();
_switchedOut = false;
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
ThreadContext *newTC = threadContexts[i];
ThreadContext *oldTC = oldCPU->threadContexts[i];
newTC->takeOverFrom(oldTC);
CpuEvent::replaceThreadContext(oldTC, newTC);
assert(newTC->contextId() == oldTC->contextId());
assert(newTC->threadId() == oldTC->threadId());
system->replaceThreadContext(newTC, newTC->contextId());
/* This code no longer works since the zero register (e.g.,
* r31 on Alpha) doesn't necessarily contain zero at this
* point.
if (DTRACE(Context))
ThreadContext::compare(oldTC, newTC);
*/
BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
// Move over any table walker ports if they exist
if (new_itb_port) {
assert(!new_itb_port->isConnected());
assert(old_itb_port);
assert(old_itb_port->isConnected());
BaseSlavePort &slavePort = old_itb_port->getSlavePort();
old_itb_port->unbind();
new_itb_port->bind(slavePort);
}
if (new_dtb_port) {
assert(!new_dtb_port->isConnected());
assert(old_dtb_port);
assert(old_dtb_port->isConnected());
BaseSlavePort &slavePort = old_dtb_port->getSlavePort();
old_dtb_port->unbind();
new_dtb_port->bind(slavePort);
}
// Checker whether or not we have to transfer CheckerCPU
// objects over in the switch
CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
if (oldChecker && newChecker) {
BaseMasterPort *old_checker_itb_port =
oldChecker->getITBPtr()->getMasterPort();
BaseMasterPort *old_checker_dtb_port =
oldChecker->getDTBPtr()->getMasterPort();
BaseMasterPort *new_checker_itb_port =
newChecker->getITBPtr()->getMasterPort();
BaseMasterPort *new_checker_dtb_port =
newChecker->getDTBPtr()->getMasterPort();
// Move over any table walker ports if they exist for checker
if (new_checker_itb_port) {
assert(!new_checker_itb_port->isConnected());
assert(old_checker_itb_port);
assert(old_checker_itb_port->isConnected());
BaseSlavePort &slavePort =
old_checker_itb_port->getSlavePort();
old_checker_itb_port->unbind();
new_checker_itb_port->bind(slavePort);
}
if (new_checker_dtb_port) {
assert(!new_checker_dtb_port->isConnected());
assert(old_checker_dtb_port);
assert(old_checker_dtb_port->isConnected());
BaseSlavePort &slavePort =
old_checker_dtb_port->getSlavePort();
old_checker_dtb_port->unbind();
new_checker_dtb_port->bind(slavePort);
}
}
}
interrupts = oldCPU->interrupts;
interrupts->setCPU(this);
oldCPU->interrupts = NULL;
if (FullSystem) {
for (ThreadID i = 0; i < size; ++i)
threadContexts[i]->profileClear();
if (profileEvent)
schedule(profileEvent, curTick());
}
}
in the base.cc
Thanks
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