I am not using DRAMSim2. In my case, the assertion error happened because dynamic instruction was not destroyed properly. As soon as the issue been taken care of, the assertion error went away.
On Tue, Apr 16, 2013 at 3:05 PM, Gedare Bloom <[email protected]> wrote: > I ran into this assertion with X86. I will try testing on the gem5 > tip, but wonder if anyone has seen and solved this issue for x86. The > other thread seems to have resulted in a fix for ARM > (http://reviews.gem5.org/r/1402/). > > -Gedare > > On Fri, Apr 13, 2012 at 1:38 AM, Andrew Cebulski <[email protected]> wrote: > > http://www.mail-archive.com/[email protected]/msg02810.html > > > > On Fri, Apr 13, 2012 at 1:31 AM, Jiachen Xue <[email protected]> wrote: > >> > >> Hi, > >> > >> I am working with X86 full system simulator using detailed cpu model. > >> > >> In my work, I need to modify the TLB structure and have to bring back > some > >> originally deferred memory accessing instructions > >> back to work. > >> > >> During the simulation, I encountered the assertion error: cpu->instcount > >> <= 1500 within src/cpu/base_dyn_inst_impl.hh : 130 > >> > >> Does anyone have a similar issue before? > >> > >> Thanks in advance, > >> > >> -- > >> Sincerely, > >> Jiachen Xue > >> > >> > >> _______________________________________________ > >> gem5-users mailing list > >> [email protected] > >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > -- > Sincerely, > Jiachen Xue >
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