Thank you so much. You do me a big favor again. On Apr 20, 2013, at 5:39 PM, Mitch Hayenga <mitch.hayenga+g...@gmail.com> wrote:
> You could add your own DPRINTF that accesses the fields of the > staticInstruction. > > Check out src/cpu/static_inst.hh. Specifically the functions > hasBranchTarget() and the two branchTarget() functions. > > > On Sat, Apr 20, 2013 at 4:24 PM, Meng Wang <m...@tupleapes.com> wrote: > Hi, all > I dumped trace of ARM benchmark in SE mode with atomic CPU. But I found > there is no branch target address for every branch instruction except "bl". > Following is a dumped branch instruction: > > 15500: system.cpu T0 : 0xa3b4 : beq : IntAlu : > > Is there any way to make the trace file show branch target address (aka. the > next pc address when this branch is taken): > > 15500: system.cpu T0 : 0xa3b4 : beq <address> : IntAlu : > > Thank you so much. > > Meng > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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