Hello, I still have an issue with the above assertion. (is in
mem/cache/mshr_queue.cc)
I am using ARM architecture. If I use only one core, then it runs withoun any
problem no matter for how many instructions I will simulate.
If I use two cores, then if I simulate for a few instructions (like until 10k
for warm-up and fast-fwd and 5 itnervals of 10k each) it plays without any
problem.
If I try to simulate for more, then the assertion is raised.
When the assertion is raised, the number of allocated entries is 5, if it
plays any difference.
I really do not know where to look at, and why that might happen?
What is freeList used for? From which part of the code, entries are deleted and
why that happen only on my large benchmarks with 2 cpus, while for one cpu, it
plays without any problem.
I can see that is being called when a cache miss happen and then an mshr miss
(from the cache_impl.hh).r
Then the allocateMissBuffer is called for the mshrQueue, which tries to call
mq->allocate. And then the assertion is raised.
Any hint on where to lack, or any way of surpassing it?
regards,
Ignatios
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