The caches aren't guaranteed to be inclusive. Ali
On May 2, 2013, at 10:15 PM, Chao Zhang <[email protected]> wrote: > Dear all, > > I met an issue when observing the cache is that I could not prove myself that > gem5 classic cache model provides cache inclusive guarantee. I looked at the > "Cache" debug trace, and found that an allocated L2 cache block will > disappear from L2, when the cache line is written back from L1 dcache, > without any eviction of this block before the writeback. The trace is that > below, please pay attention to the block whose address is b5fc0. > 348000: system.l2: ReadExReq b5fc0 miss > 348500: system.l2: ReadReq 97480 miss > 351000: system.l3: ReadExReq b5fc0 miss > 351500: system.l3: ReadReq 97480 miss > 391000: system.l3: Handling response to b5fc0 > 391000: system.l3: Block for addr b5fc0 being updated in Cache > 391000: system.l3: Block addr b5fc0 moving from state 0 to 7 > 400000: system.l3: Handling response to 97480 > 400000: system.l3: Block for addr 97480 being updated in Cache > 400000: system.l3: Block addr 97480 moving from state 0 to 7 > 425500: system.l2: Handling response to b5fc0 > 425500: system.l2: Block for addr b5fc0 being updated in Cache > 425500: system.l2: Block addr b5fc0 moving from state 0 to 7 > 434500: system.l2: Handling response to 97480 > 434500: system.l2: Block for addr 97480 being updated in Cache > 434500: system.l2: Block addr 97480 moving from state 0 to 7 > 444500: system.cpu.dcache: Handling response to b5fc0 > 444500: system.cpu.dcache: Block for addr b5fc0 being updated in Cache > 444500: system.cpu.dcache: Block addr b5fc0 moving from state 0 to 7 > > > … No b5fc0 relative management … > > > 767500: system.cpu.dcache: replacement: replacing b5fc0 with 971c0: writeback > 767500: system.cpu.dcache: Block addr 971c0 moving from state 0 to 7 > 768500: system.l2: Writeback b5fc0 miss > > The blokc b5fc0 meets a write back miss here. But it should not be a miss if > the caches guarantee inclusive between L1 and L2 cache. The build_opt is > ALPHA_MESI_CMP_directory. and I use inorder alpha cpu with 3 level caches. > > So I wanna know what's the mechanism to guarantee inclusive in classic cache > model, when there is only write back without write through? Thank you! > > Chao Zhang > School of EECS, Peking University > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
