Hello,
I have made some modification in the gem5 code so as to have 2 cores and change
the workload between them (so that in the first intervals for example run the
code in the first core and then switch to the second one and so on).
I have a question on the results I get:
Does the number of icache.ReadReq_accesses for example be the same in every
interval with the number of when running on only one core.
What I mean is this:
1. I will first run my simulation only on core A. And in every interval I have
some numbers for icache.ReadReq_accesses, for example.
2. Now I am running the simulation and I switch cores during execution. Does
the number of icache.ReadReq_accesses should be the same as in the previous
interval for each interval? Like icache.ReadReq_accesses of interval 1 of
current simulation to be equal with icache.ReadReq_accesses of itnerval 2 of
previous one, and what changes to be the simulation time.
Or am I missing something?
because If I print some traces I can see something like this for example:
ONE CORE - interval 0:
system.cpu.icache: ReadReq (ifetch) 41940 hit
system.cpu.icache: ReadReq (ifetch) 41e00 miss
system.cpu.icache: ReadReq (ifetch) 41e80 miss
....
system.cpu.icache: ReadReq (ifetch) 40e40 hit
system.cpu.icache: ReadReq (ifetch) 41e80 hit
system.cpu.icache: ReadReq (ifetch) 40e00 hit
CORE SWITCHING - interval 0:
system.cpu.icache: ReadReq (ifetch) 41940 hit
system.cpu.icache: ReadReq (ifetch) 41980 miss --different packet->addr()
--missing packet
....
system.cpu.icache: ReadReq (ifetch) 40e40 hit
--missing packet
system.cpu.icache: ReadReq (ifetch) 40e00 hit
Is it logical or I have done something wrong?
Regards,
Ignatios
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