Hello all,
I have made some changes in the gem5 (add one extra core) and the result is
that for the second core the number of dcache.WriteReq_misses is differtent in
the stats.txt with the misses that I can count in the trace file (while for the
first cpu they are the same). For example, I can see 13 misses and the measured
are 94, which is a great difference while in bigger benchmarks, I expect less
than 10.000 misses and I have over 100.000 in my stats file.
I am counting as a miss in the trace file lines like this:
system.secondmainCpu.dcache: WriteReq b58a8 miss
that come from the cache_impl.hh file where:
DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(),
pkt->req->isInstFetch() ? " (ifetch)" : "",
pkt->getAddr(), (blk) ? "hit" : "miss");
Where the counter for the stats is being incremented in order to see why the
two numbers are not equal for my second cpu.dcache?
Thanks,
Ignatios
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