Hi Serdar, Could you fire up gdb and see what mode it thinks it's in? If you could trace back to where it was set that would be helpful. I've never seen anything like this before. Do you have any changes in your gem5 repository?
Thanks, Ali On May 15, 2013, at 7:03 AM, Serdar Zafer Can <[email protected]> wrote: > Hello, > > I am running gem5 with Arm ISA and Atomic cpu model. I was running my > simulations without any errors. However I started to get this error today > after updating my Ubuntu 12.04. I downloaded and built the latest version but > still the same. There is a debug file of hello program. How can I fix this? > > Thank you. > > Serdar > > ********************************************************************************* > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > > gem5 compiled May 15 2013 12:14:37 > gem5 started May 15 2013 14:58:04 > gem5 executing on SZC-VirtualBox > command line: build/ARM/gem5.opt -r --debug-flags=ExecAll,Registers > configs/example/se.py --cpu-type=atomic -c > tests/test-progs/hello/bin/arm/linux/hello > Global frequency set at 1000000000000 ticks per second > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > 0: system.cpu.[tid:0]: Setting int reg 13 (13) to 0xbefffef0. > 0: system.cpu.[tid:0]: Setting int reg 0 (0) to 0. > 0: system.cpu.[tid:0]: Setting int reg 1 (1) to 0xbeffffa6. > 0: system.cpu.[tid:0]: Setting int reg 2 (2) to 0. > 0: system.cpu.isa: Reading From misc reg 62 (62) : 0 > 0: system.cpu.isa: Writing misc reg cpacr: 0xf00000 > 0: system.cpu.isa: Writing to misc reg 62 (62) : 0xf00000 > 0: system.cpu.isa: Reading From misc reg 14 (14) : 0 > 0: system.cpu.isa: Writing to misc reg 14 (14) : 0x40000000 > **** REAL SIMULATION **** > info: Entering event queue @ 0. Starting simulation... > 0: system.cpu.isa: Reading From misc reg 51 (51) : 0xc50008 > 0: system.cpu.isa: Reading From misc reg 55 (55) : 0 > 0: system.cpu.isa: Reading From misc reg 96 (96) : 0x98aa4 > 0: system.cpu.isa: Reading From misc reg 97 (97) : 0x40e048e0 > 0: system.cpu.isa: Reading From misc reg 76 (76) : 0 > 0: system.cpu.[tid:0]: Setting int reg 33 (33) to 0. > 0: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 0: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 0: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 0: system.cpu.isa: Reading From misc reg 51 (51) : 0xc50008 > 0: system.cpu.isa: Reading From misc reg 55 (55) : 0 > 0: system.cpu.isa: Reading From misc reg 96 (96) : 0x98aa4 > 0: system.cpu.isa: Reading From misc reg 97 (97) : 0x40e048e0 > 0: system.cpu.isa: Reading From misc reg 76 (76) : 0 > 0: system.cpu.[tid:0]: Setting int reg 12 (12) to 0x8960. > 0: system.cpu + 0: system.cpu.isa: Reading From misc reg 55 (55) > : 0 > A0 T0 : 0: system.cpu.isa: Reading From misc reg 0 (0) : 0x10 > 0x8150 : ldr r12, [pc, #36] : MemRead : D=0x0000000000008960 > A=0x817c > 500: system.cpu.[tid:0]: Setting int reg 33 (33) to 0. > 500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 500: system.cpu.[tid:0]: Setting int reg 11 (11) to 0. > 500: system.cpu + 500: system.cpu.isa: Reading From misc reg 55 (55) > : 0 > A0 T0 : 500: system.cpu.isa: Reading From misc reg 0 (0) : 0x10 > 0x8154 : mov fp, #0 : IntAlu : D=0x0000000000000000 > 1000: system.cpu.[tid:0]: Setting int reg 33 (33) to 0. > 1000: system.cpu.[tid:0]: Reading int reg 13 (13) as 0xbefffef0. > 1000: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 1000: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 1000: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 1000: system.cpu.[tid:0]: Setting int reg 1 (1) to 0x1. > 1000: system.cpu + 1000: system.cpu.isa: Reading From misc reg 55 (55) > : 0 > A0 T0 : 1000: system.cpu.isa: Reading From misc reg 0 (0) : 0x10 > 0x8158.0 : ldr r1, [sp] #4 : MemRead : D=0x0000000000000001 > A=0xbefffef0 > 1500: system.cpu.[tid:0]: Setting int reg 33 (33) to 0. > 1500: system.cpu.[tid:0]: Reading int reg 13 (13) as 0xbefffef0. > 1500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 1500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 1500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 1500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 1500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 1500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 1500: system.cpu.[tid:0]: Reading int reg 13 (13) as 0xbefffef0. > 1500: system.cpu.[tid:0]: Setting int reg 13 (13) to 0xbefffef4. > 1500: system.cpu + 1500: system.cpu.isa: Reading From misc reg 55 (55) > : 0 > A0 T0 : 1500: system.cpu.isa: Reading From misc reg 0 (0) : 0x10 > 0x8158.1 : addi_uop sp, sp, #4 : IntAlu : D=0x00000000befffef4 > 2000: system.cpu.[tid:0]: Setting int reg 33 (33) to 0. > 2000: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 2000: system.cpu.[tid:0]: Reading int reg 38 (38) as 0. > 2000: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 2000: system.cpu.[tid:0]: Reading int reg 13 (13) as 0xbefffef4. > 2000: system.cpu.[tid:0]: Setting int reg 2 (2) to 0xbefffef4. > 2000: system.cpu + 2000: system.cpu.isa: Reading From misc reg 55 (55) > : 0 > A0 T0 : 2000: system.cpu.isa: Reading From misc reg 0 (0) : 0x10 > 0x815c : mov r2, sp : IntAlu : D=0x00000000befffef4 > 2500: system.cpu.[tid:0]: Setting int reg 33 (33) to 0. > 2500: system.cpu.[tid:0]: Reading int reg 2 (2) as 0xbefffef4. > 2500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 2500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > 2500: system.cpu.[tid:0]: Reading int reg 33 (33) as 0. > panic: Flattening into an unknown mode. > @ cycle 2500 > [flattenIntIndex:build/ARM/arch/arm/isa.hh, line 132] > Memory Usage: 635508 KBytes > Program aborted at cycle 2500 > ********************************************************************************* > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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