Hi, I got stats from a detailed single-core SE simulation. I want to confirm the followings:
- All latency values are reported in pico second, right? - Demand miss is the miss due to ReadReq and WriteReq but not pre-fetching, right? - To report cache miss rate and its avg latency, which numbers I should use L2 or MSHR? What is the difference? - Is there a way to flush caches to main memory after simulation is done to account for all accesses? For example, I see the number of writes to the memory is much less than that I am actually incurring. - Is there any documentation on stats in general? Where? - Is there any specific DDR documentation on which the DDR3 model is based? Which? Thanks, Mohammed
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