Hi,
I want to configure a many core processor (6-8 cores) on an alpha processor, each of the cores should have L1,L2 private caches and L3 shared one. How do I configure this processor, I couldn’t find a way to determine which cache is private and which is shared. Thanks, Yoav Oren
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
