Hi All, 1. In the SimpleDRAM controller, it is assumed that the DRAM burst size equals to the cache line size. I think it makes more sense to use a separate variable for burst size and get rid of bytesPerCacheLine. The reason is that the DRAM controller could be connected (through a bus) to caches with different cache line sizes (e.g., a coherent cache, and a non-coherent cache/SPM for stream peripherals with large line sizes).
2. The other thing I noticed is that lines_per_rowbuffer (in SimpleDRAM.py) is set based on 64-byte cache lines. This makes the code unportable in case other cache line sizes are used. Why not using bytes per rowbuffer instead? Thanks, Amin
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