In the classic (non-Ruby) memory system, the cache hierarchy is non-inclusive, so demand misses go straight to the L1 cache. Blocks only get inserted in levels other than the L1 due to writebacks (and possibly prefetches, if you have a prefetcher associated with that level of cache).
Steve On Fri, Jun 21, 2013 at 6:03 AM, Roberto Rodríguez-Rodríguez < [email protected]> wrote: > Hello everyone, > > I am working with cache replacement policies, in the LLC I need to > distinguish between an insertion because of a writeback or because of a > miss in all cache levels. > > I thought it could be done using the packet command type (pkt->cmd == > MemCmd::Writeback). I did it but all the insertions are writebacks, there > is not an insertion because of a miss in all levels, I tested it with 1 > billion instructions of the spec2006. > > > Best Regards > > Roberto > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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