There are things other than the explicit source registers that need to be accounted for (for example flag registers).
Ali On Jun 30, 2013, at 3:08 PM, Xiangyang Guo <[email protected]> wrote: > Hi, Deal all, > > I use SE mode, ARM ISA and O3 cpu. I print out the num_src_regs, "unsigned > num_src_regs = inst->numSrcRegs(); " (src/cpu/o3/rename_impl.hh) in the > function DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid), > and I find an intertesting thing: the number of source regs are something > like 3 or 4 or 5 or 6. Then I use X86 ISA and do the same thing, and the > source regs are even something like 8. > > So I think maybe I misunderstand something, because I think the num of source > regs in one inst should be smaller. so could anyone explain this? Thanks in > advance. In addition, just want to confirm, form my understanding, the > renamed inst is micro inst? > > Regards > > Xiangyang > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
