The reason is that although the functional units latency are well
defined, the instruction are all steered to the ALU unit because their
type is wrong (inst->staticInst->_opClass is wrong). This is because the
ISA definition lacks some information. Alternatively you can set it by
hand depending on the disassembly at fetch, but this is kind of messy.
As far as I know this is the same for x86.
Arthur.
Le 05/07/2013 21:44, ali bagherian a écrit :
Hi Everyone,
Why the execution time of Mult, Div and load is the same. I now that
we can set the execution time in FuncUnitConfig.py for different
instructions. But no difference. I checked the pipeline viewer for the
output but no different in execution time. I use the Powerpc ISA. It
look like the execution time for all the instruction is 1 clock (500
tick).
Thanks,
Ali
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