Dear all, I am implementing a uarch idea on the base code of O3 model, MIPS is my target ISA. I found O3 core squashes instruction in delay slot of mispredicted branch. The squashed delay slot will be fetched again and is committed at the end of second round execution. Front-end fetches branch target after delay slot (npc of delay slot has been pointed to branch target).
For InOrder core, both mispredicted branch and its delay slot instruction are
all committed, instructions located after delay slot in program order are
squashed. Front-end will fetch from branch target.
I guess the reason for O3 model executes twice for delay slot instruction of
mispredicted branch is to unify the processing method for branch misprediction,
for both with-delay-slot ISAs and non-delay-slot ISAs.
Any comments will be appreciated.
----
' Huang He (Henry)
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