Hi Chao, I think you still have to connect the cpu ports to the l2bus. Just make sure the options.l2cache exists, in order to make the system.cpu[i].connectAllPorts(system.tol2bus, system.membus) works.
Best, On Thu, Jul 18, 2013 at 10:21 AM, Chao Zhang <zhang.c...@pku.edu.cn> wrote: > Dear Trophy, > > Thank you very much! > I'm so stupid to forget the l2option issue, to connect the cpu ports to > l4bus at the end of the configuration, just as that you pointed out. > But after this has been figured out, a new error comes. > I need a cache system with shared L2, shared l3 and shared l4. So I have > used tol2bus as to tol4bus as coherence bus. But I got the following error: > > gem5.opt: build/ALPHA/mem/cache/cache_impl.hh:1267: void > Cache<TagStore>::doTimingSupplyResponse(Packet*, uint8_t*, bool, bool) [with > TagStore = LRU, Packet* = Packet*, uint8_t = unsigned char]: Assertion > `req_pkt->isInvalidate() || pkt->sharedAsserted()' failed. > > gem5.opt: build/ALPHA/mem/cache/cache_impl.hh:1267: void > Cache<TagStore>::doTimingSupplyResponse(Packet*, uint8_t*, bool, bool) [with > TagStore = LRU, Packet* = Packet*, uint8_t = unsigned char]: Assertion > `req_pkt->isInvalidate() || pkt->sharedAsserted()' failed. > > > gem5.opt: build/ALPHA/mem/cache/cache_impl.hh:1267: void > Cache<TagStore>::doTimingSupplyResponse(Packet*, uint8_t*, bool, bool) > [with TagStore = LRU, Packet* = Packet*, uint8_t = unsigned char]: > Assertion `req_pkt->isInvalidate() || pkt->sharedAsserted()' failed. > > gem5.opt: build/ALPHA/mem/cache/cache_impl.hh:1267: void > Cache<TagStore>::doTimingSupplyResponse(Packet*, uint8_t*, bool, bool) [with > TagStore = LRU, Packet* = Packet*, uint8_t = unsigned char]: Assertion > `req_pkt->isInvalidate() || pkt->sharedAsserted()' failed. > > > It seems there something wrong with the coherence bus setting. But I don't > think the coherence buses are wrong set. So where should I focus on to fix > this issue? > > Thanks > Chao Zhang > Peking University > > > > > > 在 2013-7-17，下午11:04，Trophy Zheng <nimeitia...@gmail.com> 写道： > > HI Chao, > > Do you notice that there is : > > if options.l2cache: > system.cpu[i].connectAllPorts(system.tol2bus, system.membus) > else: > system.cpu[i].connectAllPorts(system.membus) > > in the original configuration file. > > So, if you config l4cache, there will be no options.l2cache. Thus the CPU > ports will not be connected to the tol2bus. > > I don't know if you have modified this. I just want to remind. > > Best! > > > > > On Wed, Jul 17, 2013 at 9:22 AM, Chao Zhang <zhang.c...@pku.edu.cn> wrote: > >> Dear all, >> >> I'm using gem5 to simulate 4 level caches under full system in gem5. But >> I faced an error when set up the system. >> It seams something is wrong in configurations. (I thought the error I >> sent to this mail list is nothing to do with the linux kernel. XD) >> So I want somebody could help me 1) verify the configuration I made in >> the CacheConfig.py. 2) and I want to know what's the "addtwolevelcache" in >> CPU does? I really could not understand the relationship between this >> function and the configurations in CacheConfig.py >> >> Thanks in advance! >> >> >> The configuration I wrote in CacheConfig.py is as follows: (Sorry for >> this long mail...) >> >> 49 def config_cache(options, system): >> >> 50 if options.cpu_type == "arm_detailed": >> >> 51 try: >> >> 52 from O3_ARM_v7a import * >> >> 53 except: >> >> 54 print "arm_detailed is unavailable. Did you compile the >> O3 model?" >> 55 sys.exit(1) >> >> 56 >> >> 57 dcache_class, icache_class, l2_cache_class, l3_cache_class, >> l4_cache_class = \ >> 58 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, >> O3_ARM_v7aL2, O3_ARM_v7aL2 >> 59 else: >> >> 60 dcache_class, icache_class, l2_cache_class, l3_cache_class, >> l4_cache_class = \ >> 61 L1Cache, L1Cache, L2Cache, L3Cache, L4Cache >> >> 62 >> >> 63 if options.l4cache: >> >> 64 system.l4 = l4_cache_class(clock = options.clock, >> >> 65 size=options.l4_size, >> >> 66 assoc=options.l4_assoc, >> >> 67 block_size=options.cacheline_size) >> >> 68 >> >> 69 system.tol4bus = CoherentBus(clock = options.clock, width = >> 32) >> 70 system.l4.cpu_side = system.tol4bus.master >> >> 71 system.l4.mem_side = system.membus.slave >> >> 72 >> >> 73 if options.l3cache or options.l4cache: >> >> 74 system.l3 = l3_cache_class(clock = options.clock, >> >> 75 size=options.l3_size, >> >> 76 assoc=options.l3_assoc, >> >> 77 >> block_size=options.cacheline_size) >> >> >> 78 >> >> 79 system.tol3bus = CoherentBus(clock = options.clock, width = >> 32) >> 80 if options.l3cache: >> >> 81 system.l3.cpu_side = system.tol3bus.master >> >> 82 system.l3.mem_side = system.membus.slave >> >> 83 else: >> >> 84 system.l3.cpu_side = system.tol3bus.master >> >> 85 system.l3.mem_side = system.tol4bus.slave >> >> 86 >> >> 87 if options.l2cache or options.l3cache or options.l4cache: >> >> 88 # Provide a clock for the L2 and the L1-to-L2 bus here as >> they >> 89 # are not connected using addTwoLevelCacheHierarchy. Use the >> >> 90 # same clock as the CPUs, and set the L1-to-L2 bus width to >> 32 >> 91 # bytes (256 bits). >> >> 92 system.l2 = l2_cache_class(clock=options.clock, >> >> 93 size=options.l2_size, >> >> 94 assoc=options.l2_assoc, >> >> 95 block_size=options.cacheline_size) >> >> 96 >> >> 97 system.tol2bus = CoherentBus(clock = options.clock, width = >> 32) >> 98 if options.l2cache: >> >> 99 system.l2.cpu_side = system.tol2bus.master >> >> 100 system.l2.mem_side = system.membus.slave >> >> 101 else: >> >> 102 system.l2.cpu_side = system.tol2bus.master >> >> 103 system.l2.mem_side = system.tol3bus.slave >> >> 104 >> >> 105 for i in xrange(options.num_cpus): >> >> 106 if options.caches: >> >> >> >> >> Chao Zhang >> CECA, Peking University >> >> >> >> >> >> >> >> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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