Hi Akhil, Thanks a lot for the hints. It was really helpful. Actually instead of defining individual counters for cache lines, I decided to use a multimap which is a <key,value> pair container and would make the code more neat. Also, I update the counters in lookup() method of CacheMemory, and record the cycle number when it was accessed along with the existence of the line in the cache (hit or miss).
Thanks, Mahshid On Sat, Aug 3, 2013 at 8:01 PM, Akhil Arunkumar <[email protected]> wrote: > > Hi Mahshid, > > I am guessing you want to count the number of accesses to a line while it > is in the cache. You can do this by adding counters in the > AbstractCacheEntry class which is present > in src/mem/ruby/slicc_interface/AbstractCacheEntry.hh. So every cache line > entry will have a 'hit counter'. You can update these counters from within > the setMRU function which is present in src/mem/ruby/system/CacheMemory.cc > I guess. > > I hope this helps. > > Akhil > > > > On Sat, Aug 3, 2013 at 2:23 PM, Mahshid Sedghi <[email protected]>wrote: > >> Hi everyone, >> >> I need to do a similar study as the following thread, but with Ruby >> memory system: >> http://www.mail-archive.com/[email protected]/msg06111.html >> >> I was wondering if anyone knows where to start, and which files to look >> at. >> >> Thanks a lot, >> Mahshid >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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