Hi, I have 2 questios please.
When I configure 3 or 4 levels of cache in the file CacheConfig.py, each cpu should connect to the highest level cache? or always connected to tol2bus or membus? Foe e.g. if i have 4 levels should i use : system.cpu[i].connectAllPorts(system.tol4bus, system.membus) or system.cpu[i].connectAllPorts(system.tol2bus, system.membus) ? And when i configure L2chace as a private cache, i just configure n(num of cpu) buses from each cpu to the L2cache? and the mem_side should connect either to the L3cache or memory? Thanks, Yoav Oren
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