Using the atomic cpu, with fastmem, it takes about 7 days for most of the benchmarks to finish on the "train" input set. This was with the ARM ISA on a bunch of old 2.4 ghz opterons.
I calculated it out once using other paper's presented instruction counts, and running the whole reference input set would take 1-2 months I think. This is why you should use simpoints for SPEC, it is unfeasible simulate the whole thing. You can generate checkpoints/simpoints using the atomic cpu, and run smaller portions later on a detailed cpu. On Thu, Aug 29, 2013 at 3:46 AM, 张 磊 <[email protected]> wrote: > It seems so, but I'm not sure if it is just too slow. > > > 在 2013-8-29，下午4:41，Hao Wang <[email protected]> 写道： > > > I guess for most of the spec benchmarks it never finishes? > > > > Bonzi > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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