Hi, I want to split L2 into 2 parts, one part for connecting L1 I Cache and one for connecting L1 D Cache, and then connected the spited cache into memory directory. After searching the mailing list, I cannot find the answer. In fact, I tried to make 2 L2 caches(L2_i for I cache and L2_d for D cache, and toL2_iBus and toL2_dBus) and then connect them with L1 cache and memBus in /confis/common/CacheConfig.py file, but it seems that the system cannot realize my "l2_i" cache and "l2_d" cache.
So could any one give me some advice? Any hint is appreciable. Regards Xiangyang
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
