Hi Zhiguo, There are two concepts here, cache states and the state of a exclusive monitor (that checks if the cache line has been written since it was put in the monitor) .While these concepts can be joined, they don't need to be.
So, you could probably add the NeedsExclusive attribute and it should work, but it doesn't strictly need to (it will get cache exclusive state when the store is sent to the caches). Ali On Sep 20, 2013, at 12:30 AM, GE ZHIGUO <ge.zhi...@huawei.com> wrote: > Hi, > > ARM ldrex instruction use LoadLockedReq (mem/packet.cc) in GEM5. > If I am not wrong, according to ARM document, ldrex will make cache line in > exclusive state. > But LoadLockedReq does NOT have NeedsExclusive attribute now. > does LoadLockedReq packet miss NeedsExclusive attribute or should ldrex use > another type packet? > > Thanks! > > Zhiguo > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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