How does the register interact with the rest of the cache controller then? Also can you dynamicly allocate additional states to each cache lines (For the variable child states I mentioned previously)?
Yanqi Zhou <[email protected]> wrote: >It saves the in-flight requests that has a miss in the cache, with a tag field >and value field. When the value is available, it dequeue the corresponding >entry of request. >________________________________ >From: Alex Tomala [[email protected]] >Sent: Wednesday, October 02, 2013 10:11 AM >To: gem5 users mailing list; Yanqi Zhou >Subject: Re: [gem5-users] What is the TBE in Ruby? > >How is the register used? My assumption is that it is intialized when there is >a memory request, but then what purpose does it serve afterwards? > >The cache coherence protocol that I am using has more then one state in it. It >has the regular cache state, a parent cache state, and a variable amount of >child states that depends on an input variable. Do you know if there is anyway >I can implement a cache coherence architecture with multiple states and if I >can have a variable number of duplicate states? > >- Alex > >From: Yanqi Zhou <[email protected]> >To: gem5 users mailing list <[email protected]> >Sent: Wednesday, October 2, 2013 9:50:09 AM >Subject: Re: [gem5-users] What is the TBE in Ruby? > >It is the registers for non-blocking cache, which allows you to have multiple >cache accesses when there is a memory request in-flight. >________________________________________ >From: [email protected]<mailto:[email protected]> >[[email protected]<mailto:[email protected]>] on behalf of >Alex [[email protected]<mailto:[email protected]>] >Sent: Wednesday, October 02, 2013 9:38 AM >To: GE ZHIGUO; gem5 users mailing list >Subject: Re: [gem5-users] What is the TBE in Ruby? > >Hello, > >Taking a quick look, I can't see if it is neccessory for the cache coherence >protocol. I am wondering if you do need it or not and what does the MSHR/TBE >do. > >- Alex > >GE ZHIGUO <[email protected]<mailto:[email protected]>> wrote: > >>Hi, Alex >> >>I think that it is Miss-Status Handling Registers (MSHR) in cache. >> >>Regards >>Zhiguo >> >>From: [email protected]<mailto:[email protected]> >>[mailto:[email protected]<mailto:[email protected]>] On >>Behalf Of Alex Tomala >>Sent: Wednesday, October 02, 2013 8:07 AM >>To: [email protected]<mailto:[email protected]> >>Subject: [gem5-users] What is the TBE in Ruby? >> >>Hello, >> >>I am working on making a new cache coherence protocol (ruby) and I am just >>wondering what the TBE is for. It seems to be used when a Miss event happens >>but I just want to be sure that is true. >> >>- Alex >_______________________________________________ >gem5-users mailing list >[email protected]<mailto:[email protected]> >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >_______________________________________________ >gem5-users mailing list >[email protected]<mailto:[email protected]> >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
