Hi all,
I am modifying gem5 to have different latency for read and write access
for cache memory.
Now to validate it, I want to check in a simuation if different latency
for read and write access is taken in account.
I tried to use the CommMonitor but I didn't manage to use it.
Is there an other way to check the cache latency in a simulation ?
Thank you very much.
Sophiane
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