[gem5-users] Increasing write latency has not significant impact on sim_seconds

[senni sophiane]

Hi everybody,

I ran some simulations increasing the write latency (only) for caches 
(L1 and L2) but there is no significant impact on execution time 
(sim_seconds in stats.txt).
But when I increase read latency (only) for caches, significant change 
on sim_seconds can be noticed.

Is it normal ? If yes, why ? And how can I include the effect of write 
latency into the running application ?

Thanks

Sophiane
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