Thanks Henry, I see that.

Regards,
Yuan

On 25 Oct, 2013, at 7:20 PM, "Huang, Henry" <henry.hu...@amd.com> wrote:

> Yuan,
>  
> O3CPU does support STLF. You may see function
>  
> LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, 
> uint8_t *data, int load_idx)
>  
> in source file lsq_unit.hh for reference.
>  
> Henry
>  
> ----
>        '
>       /-\\          CPU/CCNUMA Microarchitect
>      /---\'\
>     /-----\'`\      X86/ARMv8/MIPS Microarchitecture
>    /-------\'`,\    ccNUMA Node Controller Architecture
>   /---------\' ,`7  Intel QPI Cache Coherence Protocol
> /-----------\' /   http://www.linkedin.com/in/huanghe
> /-------------\/    http://dl.acm.org/citation.cfm?id=285930
>  
> -----Original Message-----
> From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On 
> Behalf Of GE ZHIGUO
> Sent: Friday, October 25, 2013 5:08 PM
> To: gem5 users mailing list
> Subject: Re: [gem5-users] O3CPU LSQ store-to-load forwarding
>  
> Yes, it supports if I did not misunderstanding GEM5 source code.
> This is a very basic functionality of store queue.
> Anyone please correct me if I am wrong. Thanks!
>  
> Zhiguo
>  
> -----Original Message-----
> From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On 
> Behalf Of Yuan Yao
> Sent: Friday, October 25, 2013 5:00 PM
> To: gem5 users mailing list
> Subject: [gem5-users] O3CPU LSQ store-to-load forwarding
>  
> Hi, all,
>  
> Does the O3CPU LSQ support store-to-load forwarding? From the L1 memory 
> trace, I can see a load issued to memory for exactly the same address (no 
> only the cacheline address) to an outstanding store.
>  
> Regards,
> Yuan
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>  
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