Hello everyone!
I've been trying to implement a third level of cache memory with the MESI
protocol. I decided to use the MOESI_hammer-cache.sm file as reference and
create another cache memory (which I called L12cacheMemory) in the
MESI_CMP_directory-L1cache.sm file. The last level cache will still be
implemented by the MESI_CMP_directory-L2cache.sm file which I'm not modifying.
I want to deal with the coherence protocol in the L12cacheMemory while L1I &
L1D are just subsets of the data contained in L12 (L1I, L1D & L12 private. L2
shared).
When receiving messages, I'd like to evaluate first the L12 memory and then,
depending on the type of message forward it to L1I or L1D. So in the part where
the mandatory queue is read, I have something like
Entry L12cache_entry := getL12CacheEntry(in_msg.LineAddress);
.
.
if(is_valid(L12cache_entry)){
...
}else{
if(L12cacheMemory.cacheAvail(in_msg.LineAddress)){ //L12
doesn't have the line, but there is space for it
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress, L12cache_entry, L12_TBEs[in_msg.LineAddress]);
}
}
At the begining of the execution the L12cache_entry won't be valid and the data
should be allocated in L12, however I'm getting the following error:
gem5.opt: build/X86/mem/ruby/system/CacheMemory.cc:244: AbstractCacheEntry*
CacheMemory::allocate(const Address&, AbstractCacheEntry*): Assertion
`!isTagPresent(address)' failed.
Apparently the tag in the cache_entry is not present. How can I make it present?
I tried to use the same program structure that is used for deciding if the data
corresponds to L1I or L1D but in those cases I don't get an error.
What is missing? Does anyone knows a better way to do it?
I know this is a long question, but any help will be appreciated.
Thank you so much
--
Alberto Javier Naranjo-Carmona
M.S. Computer Engineering
Texas A&M University, College Station, TX
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