Thanks Andreas for your reply.
Adding latency to the writes can have an impact if I reduce the
write_buffer_size ?
Cordialement / Best Regards
SENNI Sophiane
Ph.D. candidate - Microelectronics
LIRMM - www.lirmm.fr
Le 04/11/2013 14:59, Andreas Hansson a écrit :
Hi Sophiane,
By the time you look a the write packet it has already been responded to
and consequently deleted. When a write arrives we put it in the write
queue and send the response straight away. If you want to know if the
DRAMPacket is a write look at dram_pkt->isRead. It¹s worth noting that
adding latency to the writes will probably not have any impact for the
very reason stated above.
Andreas
On 04/11/2013 13:45, "senni sophiane" <[email protected]> wrote:
Hi everybody,
I am trying to differentiate latency for read and write access in
SimpleDRAM adding a new parameter tCL_write.
When I use a " if(dram_pkt->pkt->isWrite()) " statement in
simple_dram.cc (function SimpleDRAM::estimateLatency), I have a
segmentation fault when booting in FS or SE mode.
I don't know what is the problem. Does someone have an idea why it
doesn't work ?
Thank you.
--
Cordialement / Best Regards
SENNI Sophiane
Ph.D. candidate - Microelectronics
LIRMM - www.lirmm.fr
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