Dear all, I am very new to this simulator environment. I have some basic queries related to the simulator usage.
Could you please help me to know 1) How easy it is to modify the system structure to a format with L1 caches making a bus based cluster with L2 caches making directory interconnection. L2 cache with distributed directory based coherency structure variation as per my internal use. (to what extend I can expect the architectural configurability for NoC based MPSoC architecture like Ruby, particularly for cache, coherence and memory subsystems) 2) Is there any documentation on the recent changes and configuration possibilities for cache/memory subsystem of Gem5 simulator and the extend of support. Looking forward to hearing from you, Thank you in advance, Preethi, Technical University of Munich, Germany.
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