You need to change the ISA files as well. Search for an existing pseudo inst in src/arch/arm/isa/
Ali On Nov 11, 2013, at 9:10 AM, JIN MIN KIM <[email protected]> wrote: > Hi all, > > I'm working on extending the ARM ISA by adding pseudo instructions. > I choose 0x56 as the opcode. > I've already added new operation in following files. > src/sim/pseudo_inst.cc > src/sim/pseudo_inst.hh > util/m5/m5op.h > util/m5/m5op_arm.S > util/m5/m5ops.h > > However, the following panic is occurred. > > command line: build/ARM/gem5.opt configs/example/se.py -n 2 -c > tests/test-progs/add/add;tests/test-progs/add/add > Global frequency set at 1000000000000 ticks per second > **** REAL SIMULATION **** > info: Entering event queue @ 0. Starting simulation... > Hello world! > Hello world! > panic : Attempted to execute unknown instruction (inst 0xee560110) > @ cycle 3597000 > [invoke:build/ARM/arch/arm/faults.cc, line 192] > > If you have any suggestion, please let me know. > Thanks! > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
