you should implement a stream prefetcher with maximum 8 streams and set your prefetch distance as 8 cache lines
On Mon, Dec 2, 2013 at 10:16 PM, Fernando Endo <[email protected]>wrote: > Hello, > > If you're looking for stride prefetchers, they exist: For example in the > O3_ARM_v7a.py configuration file, in the L2 cache: > prefetcher = StridePrefetcher(degree=8, latency='1.0ns') > > By the way, could someone help me to configure the stride prefetcher for > the Cortex-A9 (in its L1-D cache)? The Cortex-A9 manual says: > > 1) can monitor and prefetch up to eight independent data streams > 2) maximum stride of 8 cache lines > > By default, the stride prefetcher has 100 entries in its buffer, so how > the above info is related to the prefetcher buffer size and degree? > > Regards, > > -- > Fernando A. Endo, PhD student and researcher > > Université de Grenoble, UJF > France > > > > 2013/11/30 jerry yin <[email protected]> > >> Hi, >> >> I'm relatively new here. Just wondering if there is DRAM prefetcher in >> gem5? I do find a folder /src/mem/cache/prefetch, but the C++ class seems >> to be all cache prefetchers. >> >> If there is no DRAM prefetcher, do you have any advice in implementing >> it? What file should I aim to modify? >> >> Thanks! >> Jerry >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- *thanks®ards* *BISWABANDAN* http://www.cse.iitm.ac.in/~biswa/ “We might fall down, but we will never lay down. We might not be the best, but we will beat the best! We might not be at the top, but we will rise.”
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