MSHR, non blocking cache, memory level parallelism. On Dec 8, 2013 1:13 AM, "Hossein Nikoonia" <[email protected]> wrote:
> Dear List, > > I am running an experiment with gem5 in X86 + SE + Classic Memory. > The system has two cpus and runs two workloads. The workload is very > simple. It accesses memory in each cycle and (almost) each memory access > misses in L2 (miss ratio = 0.999985 as reported by > system.l2.overall_miss_rate::total). > However, overall miss latency of l2 (system.l2.overall_miss_latency::total > = 24583668000) is almost 2x sim_ticks (which is 14763786000) !!!! > > Any idea how did this happened? Am I missing something? > > Thank you in advance > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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