Thanks very much.

I see the cpu/o3/iew_impl.hh as follows. In line 01071, I want to modify the 
logic. I want to count the number of cycles when I issue a memory request in 
LSQ, rather than the number of requests. How to implement it?


Please see following lines and the bold notes, then give some advice. Thank you 
in advance.


cpu/o3/iew_impl.hh


                       if (inst->isLoad()) {  
01064             DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
01065                     "encountered, adding to LSQ.\n", tid);
01066 
01067             // Reserve a spot in the load store queue for this
01068             // memory access.
01069             ldstQueue.insertLoad(inst);
01070 
01071             ++iewDispLoadInsts;                   // Note: Here I want to 
count the number of cycles when I issue a memory request in LSQ, rather than 
the number of requests. How to implement it?
01072 
01073             add_to_iq = true;
01074 
01075             toRename->iewInfo[tid].dispatchedToLSQ++;
01076         } else if (inst->isStore()) {
01077             DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
01078                     "encountered, adding to LSQ.\n", tid);
01079 
01080             ldstQueue.insertStore(inst);
01081 
01082             ++iewDispStoreInsts;
01083 
01084             if (inst->isStoreConditional()) {
01085                 // Store conditionals need to be set as "canCommit()"
01086                 // so that commit can process them when they reach the
01087                 // head of commit.
01088                 // @todo: This is somewhat specific to Alpha.
01089                 inst->setCanCommit();
01090                 instQueue.insertNonSpec(inst);
01091                 add_to_iq = false;
01092 
01093                 ++iewDispNonSpecInsts;
01094             } else {
01095                 add_to_iq = true;
01096             }



At 2013-12-10 15:01:21,"Amin Farmahini" <[email protected]> wrote:

Count the number of cycles you issue a memory request in LSQ.




On Tue, Dec 10, 2013 at 12:41 AM, Yuhang Liu <[email protected]> wrote:

Thanks for your reply. 
I know the number of loads and stores issued in a given period. But what I 
really want to know is not this.  I wonder how many cycles in which a new load 
or store request is issued. This number cannot be got via dividing # the number 
of loads and stores by # the number of cycles, since maybe more than one load 
or store be issued in the same cycle. 


Could you give some advice?


At 2013-12-10 13:40:43,"Amin Farmahini" <[email protected]> wrote:

If you are using O3, you can add some counters in LSQ to count the number of 
loads and stores issued. That is fairly simple.

You may also take a look at stats file. You may be able to extract that 
information from stats even w/o modifying the code.



Thanks,
Amin




On Mon, Dec 9, 2013 at 11:41 AM, Yuhang Liu <[email protected]> wrote:

Hi,
Is there a metric to show "the frequency of memory requests being issued each 
cycle"?


That means, for example, in 10 cycles, there are 6 cycles in which there is a 
new memory request be issued, then "the frequency of memory requests being 
issued each cycle" is 60%.


How can I know it in GEM5 output?


John



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