Dear All, I am trying to design my own accelerator in gem5, and I would like to know if there is any component already available which I can instantiate and modify? I would need a component with a Master Port and a Slave Port to be able to both Write/Read to address space of this accelerator (from the main processors), also Write/Read to main memory from inside this accelerator.
Thanks in advance, -- Erfan Azarkhish Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna DEI - University of Bologna, Italy
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