Hi I have the same problem, I set L1 and L2 size to 64B, I checked the trace file and I figured out on a write-back miss replacement actually occurs in both cases ZhengWu mentioned below, but it does not appear in trace file sometimes, I thought mshr and write-buffers cause this, so I set mshr, targets per mshr and write-buffers to 1, but I still cant see replacement in trace file sometimes since I know replacement actually occurs. Did anyone encounter the same problem and shed some light on this?
Thank you On Sun, 21 Oct 2012 Zheng Wu wrote: Hi All, I am trying to understand writeback miss and hits. Right now, I only have a single core with L1 and L2 in my simulation, so there is no coherency b/w cores. I want to extract from the simulation the traces for the last level cache. More specifically the misses that leads to memory accesses, so I am trying to extract the memory requests from the traces. I don't quite understand the behaviour of writebacks. My understanding is that when a block is dirty and if it's being replaced, then we must write this back to main memory. So what's the meaning of hits and misses? I noticed from the trace that when there is a writeback hit, no actual replacement occurs. However, for writeback misses, the replacement occurs some of the time but not others, why is this the case? shouldn't we always replace the dirty block? Here is two example of traces where one does replacment and one does not: Replacement occurs: --------------------------------------------- 20004092000: system.cpu.dcache: ReadReq 109e380 miss 20004093000: system.l2: ReadReq 109e380 miss 20004145000: system.cpu.dcache: replacement: replacing 108e380 with 109e380: writeback 20004147000: system.l2: Writeback 108e380 miss 20004147000: system.l2: replacement: replacing e8e380 with 108e380: writeback ------------------------------------------------------------------ No Replacment: ---------------------------------------------------------- 960663000: system.cpu.dcache: WriteReq 14bbc00 miss 960664000: system.l2: ReadExReq 14bbc00 miss 960716000: system.cpu.dcache: replacement: replacing 10abc00 with 14bbc00: writeback 960718000: system.l2: Writeback 10abc00 miss ---------------------------------------------------------------- Many Thanks, Zheng Wu
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