Hello, I would say that this issue is specific to the SE mode in gem5. It seems that they copy-paste the binaries in the memory for each core (even if the binary is the same).
Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2014-01-26 kunta Zhang <[email protected]> > I'm using gem5 to simulate a multi core system in which each core executes > the same workload with a shared low level instruction cache. > > I found that gem5 will assign the workload of each core a different > physical address in memory even if the workload is exactly the same! That > behavior is unexpected for me because I'm studying the sharing mechanism of > the shared instruction cache in the system. > > What I want is that the sharing workload will be place in a single, shared > address in the shared instruction cache and the memory. > > For example, in this simple run: > build/ALPHA/gem5.opt --debug-flags=TLB,Cache,Bus,Fetch > configs/example/se.py --l2cache --cpu-type=timing -n 4 --caches > > --cmd="tests/test-progs/hello/bin/alpha/tru64/hello;tests/test-progs/hello/bin/alpha/tru64/hello;tests/test-progs/hello/bin/alpha/tru64/hello;tests/test-progs/hello/bin/alpha/tru64/hello" > > Gem5 will assign each "hello" binary to a different physical address. > > Can anyone help? Thanks ahead! > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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