Hi all As I change tRCD of DDR3_1600_x64 in src/mem/SimpleDRAM.py (and rebuilding) , I do not see any significant change in simulation time. I expected that when no caches are used simulation time should increase as tRCD of DRAM increases, because every memory request has to be served by main memory. The command line I use is: ./build/ALPHA/gem5.opt ./configs/example/fs.py --cpu-type=timing --mem-size=512MB --mem-type=DDR3_1600_x64 --disk-image=/disks/linux-parsec-2-1-m5-with-test-inputs.img --script=blackscholes_2c_simsmall.rcS. Can anyone please tell me how I can see latency effects of DRAM on simulation time.
Thanks Shivam
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