I found my problem, I want to test a system with a main memory with a write latency bigger than a read latency, similar to PCM. So I split the TCL latency into TCLrd and TCLwr in the estimateLatency method (simple_dram.cc), after a while of simulation I got the Seg Fault error. I tested this change with the spec in SE mode and worked perfect. Thanks Rodrigo
From: [email protected] To: [email protected] Date: Tue, 18 Feb 2014 09:38:33 +0000 Subject: Re: [gem5-users] Parsec Seg Fault Hi Rodrigo, Is there any chance you could run this through e.g. gdb and determine where the segfault occurs? Also, could you provide more detail as to what it is you are running? It could be that the memory controller is giving you issues, or simply that the timing behaviour changes as a result of using a different memory. It would be good to get to the bottom of it. Andreas From: Rodrigo Reynolds Ram�rez <[email protected]> Reply-To: gem5 users mailing list <[email protected]> Date: Tuesday, 18 February 2014 02:02 To: gem5-users <[email protected]> Subject: [gem5-users] Parsec Seg Fault Hello everyone, I don't know why when I define a memory type different from simple_mem I get a Seg Fault. For example with --mem-type=ddr3_1600_x64. I am trying to simulate the Parsec using the disk image for alpha from University of Texas with a classic memory model, this problem always happens with ferret. That is very strange. Thanks in advance Rodrigo -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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