Siddharth Nilakantan <sid.nil <at> gmail.com> writes: > > Hi, > I have Splash-2 compiled with m5threads for the X86 architecture. I'm trying to run it with the classic memory system, in SE mode, with the TimingSimpleCPU. I'm not sure these runs are making forward progress. They have been running for over 2 days. Looking at a trace I see a lot of repetitive addresses being generated. > > > Here is the exact command I used: ~/gem5-stable- 6a043adb1e8d/build/X86_MESI_CMP_directory/gem5.opt ~/gem5-stable- 6a043adb1e8d/configs/example/se.py --l2cache --l1d_size=32kB --l1d_assoc=4 - -l1i_size=32kB --l1i_assoc=4 --l2_size=256kB --l2_assoc=8 -- cacheline_size=64 --num-cpus=4 -- cmd=/home/DREXEL/sn446/ECEC414/X86/splash2/splash2/codes/kernels/lu/non_cont iguous_blocks/LU --options=-p4 -t --cpu-type=timing > > > Has anyone encountered this issue before? Has anyone run this particular configuration? > > When I switch to the AtomicSimpleCPU all my runs finish very quickly. > > > Regards, > Sid > > > _______________________________________________ > gem5-users mailing list > gem5-users <at> gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Hey sid, I want to know the procedure for compiling the Spalsh-2 with m5threads for X86 architecture pl. guide. - AKT _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
