As far as I know, gem5 classic cache is non-inclusive. I cannot speak for ARM caches.
Thanks, Amin On Sat, Mar 1, 2014 at 8:46 PM, Peng Wei <[email protected]> wrote: > Hi there, > > I was wondering if anybody could help me clarify which kind of cache > mechanism adopted for gem5's ARM L2 Cache. Is it strictly inclusive, > exclusive or neither? > > According to the trace I generated from gem5's ARM simulator, I found: > > (1) for one address, if there is a "ReadReq" and hit a cache line in L2, > the next few accesses will continue to hit that line. That seems like it is > not totally exclusive. > > (2) for one address, if there is a "ReadExReq" which incurred by a write > miss, the next accesses will become "miss". It seems that there are some > lines in L1 but not in L2, which means that it is not strictly inclusive. > > If all of my observation is true, the L2 Cache in gem5's ARM simulator is > neither inclusive nor exclusive. Is it really what ARM chips do now? Why > the L2 Cache is simulated like this? > > Thanks very much. > > Best regards, > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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