Hi, I am trying to switch between two detailed ARM cpu models using repeat-switch for bbench. I am hitting the assert(!memReq) assertion in drainSanityCheck() after around around 3 seconds (300 switches) of simulation time. I looked at the code but could not think of a situation where drain would be signalled before a memReq is created. I am going to look further but it would be very helpful if some one already has a patch/solution to this.
My gem5 version is pretty recent from Jan 2014. The cores have DFS implemented. I am avoiding other drainSanityCheck() assertions by adding a condition to check if the stage is blocked before signalling drain. Thanks Srini _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
