[gem5-users] Why is CommMonitor not working?

[Pei Luo]

Hi, all,

I get some problem with CommMonitor, I add a monitor between L1D and CPU as
following:

1. In BaseCPU.py:
   add: from CommMonitor import *

modify the L1D cache connection:
    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
        self.icache = ic
        self.dcache = dc
        self.icache_port = ic.cpu_side
        #self.dcache_port = dc.cpu_side

        # Add the following three lines to
        self.L1MONITOR = CommMonitor(trace_file = "cpu.ptrc")
        self.dcache_port = self.L1MONITOR.slave
        self.L1MONITOR.master = dc.cpu_side

        self._cached_ports = ['icache.mem_side', 'dcache.mem_side']

2. Then compile and run, I can see the monitor is there in config.ini

[system.cpu.L1MONITOR]
type=CommMonitor
bandwidth_bins=20
burst_length_bins=20
clk_domain=system.cpu_clk_domain
disable_addr_dists=true
disable_bandwidth_hists=false
disable_burst_length_hists=false
disable_itt_dists=false
disable_latency_hists=false
disable_outstanding_hists=false
disable_transaction_hists=false
eventq_index=0
itt_bins=20
itt_max_bin=100000
latency_bins=20
outstanding_bins=20
read_addr_mask=18446744073709551615
sample_period=1000000000
trace_file=cpu.ptrc
transaction_bins=20
write_addr_mask=18446744073709551615
master=system.cpu.dcache.cpu_side
slave=system.cpu.dcache_port




But the problem is that the output is empty, does anyone know what's the
problem? Is there any good method to monitor the L1D cache? Thanks a lot!


-- 
Pei Luo 骆培

Electrical and Computer Engineering, Northeastern University

Phone: (001) 617-849-3485

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