On Apr 17, 2014, at 3:36 AM, Kuk-Hwan Kim <[email protected]> wrote:
> > Dear Gem5 community, > > I have simple two questions. > > 1. Do we have gem5 models which is similar to Cortex-M3 core + on-chip SRAM > + on-chip flash? If not, what would be the most efficient building out of > currently available component sets? Cortex-M3 has in-order CPU. Right now gem5 only support the ARMv7-A and ARMv8-A instruction profiles. There would be some missing functionality for the ARMv6-M profile. Our SimpleMemory class would look quite a bit like any memory with a deterministic access time provided you configured the latencies to be similar and a timing simple cpu is a very simple machine that always delays, it’s not in any way a model of a cortex-m, but it may be sufficient depending on what you’re trying to do. > > 2. PARSEC 3.0 for ARM > > I am looking forwards to have PARSEC 3.0 benchmark binaries ported to > ARMv7a. > > As described in the following website, > http://gem5.org/PARSEC_benchmarks > > arm-system-2011-08.tar.bz2 supposed to have 11 applications compiled to > ARMv7 binaries. But I couldn't find the benchmark binaries inside the disk > image file? Did I download wrong file or the post is not currently > reflecting reality? I believe the key word is that they “can be” compiled, not that they are and placed on the disk image. See http://gem5.org/DaCapo_benchmarks for a quick way (chrooting) to compile binaries from a disk image if you have an ubuntu system. > > Any information or recommendation would be greatly appreciated > > Regards > Kuk-Hwan > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
