Dear Gem5 community, I am struggling with reading through stats-file. Here I have listed questions and thought which came across my mind when I went through L2 cache-related paraemters. If you could provide any information, intuition, or insight, it would be greatly help me understand stats.file.
Thank you for your help in advance Regards Kuk-Hwan (1) I was wonder what is system.l2.tags.taginuse and system.l2.tags.sampled_refs parameters? Could you provide detailed description of those parametres? (2) system.l2.tags.occ_blocks - what is occupied blocks per requestor?. What is meaning of requestor and what is unit of occupied blocks? Does unit of occupied block means cache line which is 64Byte? Usual value for avg. occupied blocks per requestor is about 56 ~ 1122. I was wonder what is substanc of request which is related with that big occupied blocks. (3) It might be silly question, how does cache occupancy is calculated, and what is the implication of the cache occupancy? (4) system.l2.tags.occ_task_id_blocks::1023, 1024, 1024::0, 1024::1, what is 1023, 1024 and what is 1024::1, 1024::2? And generally occpied blocks per task ID is smaller than occupied blocks per requestor? It looked like one requestor comprised of several taks ID. Then, what is real substance of requestor and task ID in terms of programmer point of view? If somebody can help me out by using simple C code example, it will greatly help me out. (5) when I look at the cache occupancy on taskID1023 and ID1024, the value is significantly different. one is 0.001343 and the other one is 0.981689. Why two different task ID can have significant differnt cache occupancy?. (6) system.l2.tags.tag_accesses and system.l2.data_acess values are same. how come those numbers can be same although one is accessed to tags and others accessed to data? Or, cache access is just supposed to go through tag access first and then data access? in this case, is it possible to bypass tag access and go to data access directly? (It doesn't sound right to me though, how cache system can determine it is hit without comparing tags?) (7) system.l2.Writeback_hits::writebacks and system.l2.write_hits::total values are same as 19143276. then writeback_hit_total has only one member function? or I am missing other memberfunction of writeback_hits::total? (8) In regards to UpgradeReq_hits, who/what is trying to update what information? (9) In regards to ReadEx_hits, It sounded like read request come from external? where is the readEx come from? (10) In regards to demand_hits and overall_hits, their value is exactly same. What would be the case in which they are differnt in values. (11) what is the difference between system.l2.blocked_cycles::no_mshrs system.l2.blocked_cycles:no_targets versus system.l2.blocked::no_mshrs, system.l2.blocked::no_targets versus system.l2.avg_blocked_cycles::no_mshrs, system.l2.av_blocked_cycles::no_targets ? what is the difference between them they are all both 0 and have same comments. (12)system.l2.fast_writes, what is this fast_writes means? (13)system.l2.cache_copies, what is this cache_copies menas? (14)In regards to system.tol2bus.throughput, data_through_bus, what is this number? is this bus transaction referring to bus transaction between l1 and l2? if then, l1 has l1 data, l1 instruction, I would like to know what kinds of Throughput and data is accounted into this parameter? (15)In regards to system.iobus.throughput and iobus.data_through_bus, what is throughput and data traffic which go through this parametres? What kind of traffic usually go through iobus? --------------------------- Except from stats.txt -------------------------- system.l2.tags.replacements 13496677 # number of replacements system.l2.tags.tagsinuse 8112.853371 # Cycle average of tags in use system.l2.tags.total_refs 68003485 # Total number of references to valid blocks. system.l2.tags.sampled_refs 13496677 # Sample count of references to valid blocks. system.l2.tags.avg_refs 5.038535 # Average number of references to valid blocks. system.l2.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2.tags.occ_blocks::writebacks 1560.926884 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu.dtb.walker 141.432547 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu.itb.walker 27.312445 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu.inst 1595.305186 # Average occupied blocks per requestor system.l2.tags.occ_blocks::cpu.data 4787.876309 # Average occupied blocks per requestor system.l2.tags.occ_percent::writebacks 0.190543 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu.dtb.walker 0.017265 d# Average percentage of cache occupancy system.l2.tags.occ_percent::cpu.itb.walker 0.003334 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu.inst 0.194739 # Average percentage of cache occupancy system.l2.tags.occ_percent::cpu.data 0.584458 # Average percentage of cache occupancy system.l2.tags.occ_percent::total 0.990339 # Average percentage of cache occupancy system.l2.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2.tags.occ_task_id_blocks::1024 8066 # Occupied blocks per task id system.l2.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id system.l2.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id system.l2.tags.age_task_id_blocks_1024::1 900 # Occupied blocks per task id system.l2.tags.age_task_id_blocks_1024::2 555 # Occupied blocks per task id system.l2.tags.age_task_id_blocks_1024::3 6178 # Occupied blocks per task id system.l2.tags.age_task_id_blocks_1024::4 220 # Occupied blocks per task id system.l2.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id system.l2.tags.occ_task_id_percent::1024 0.984619 # Percentage of cache occupancy per task id system.l2.tags.tag_accesses 1395501681 # Number of tag accesses system.l2.tags.data_accesses 1395501681 # Number of data accesses system.l2.ReadReq_hits::cpu.dtb.walker 29704009 # number of ReadReq hits system.l2.ReadReq_hits::cpu.itb.walker 1367268 # number of ReadReq hits system.l2.ReadReq_hits::cpu.inst 9922588 # number of ReadReq hits system.l2.ReadReq_hits::cpu.data 22153368 # number of ReadReq hits system.l2.ReadReq_hits::total 63147233 # number of ReadReq hits system.l2.Writeback_hits::writebacks 7828991 # number of Writeback hits system.l2.Writeback_hits::total 7828991 # number of Writeback hits system.l2.UpgradeReq_hits::cpu.data 1179 # number of UpgradeReq hits system.l2.UpgradeReq_hits::total 1179 # number of UpgradeReq hits system.l2.ReadExReq_hits::cpu.data 1553905 # number of ReadExReq hits system.l2.ReadExReq_hits::total 1553905 # number of ReadExReq hits system.l2.demand_hits::cpu.dtb.walker 29704009 # number of demand (read+write) hits system.l2.demand_hits::cpu.itb.walker 1367268 # number of demand (read+write) hits system.l2.demand_hits::cpu.inst 9922588 # number of demand (read+write) hits system.l2.demand_hits::cpu.data 23707273 # number of demand (read+write) hits system.l2.demand_hits::total 64701138 # number of demand (read+write) hits system.l2.overall_hits::cpu.dtb.walker 29704009 # number of overall hits system.l2.overall_hits::cpu.itb.walker 1367268 # number of overall hits system.l2.overall_hits::cpu.inst 9922588 # number of overall hits system.l2.overall_hits::cpu.data 23707273 # number of overall hits system.l2.overall_hits::total 64701138 # number of overall hits system.l2.ReadReq_misses::cpu.dtb.walker 201918 # number of ReadReq misses system.l2.ReadReq_misses::cpu.itb.walker 34225 # number of ReadReq misses system.l2.ReadReq_misses::cpu.inst 1937307 # number of ReadReq misses system.l2.ReadReq_misses::cpu.data 8370020 # number of ReadReq misses system.l2.ReadReq_misses::total 10543470 # number of ReadReq misses system.l2.UpgradeReq_misses::cpu.data 48347 # number of UpgradeReq misses system.l2.UpgradeReq_misses::total 48347 # number of UpgradeReq misses system.l2.ReadExReq_misses::cpu.data 2969402 # number of ReadExReq misses system.l2.ReadExReq_misses::total 2969402 # number of ReadExReq misses system.l2.demand_misses::cpu.dtb.walker 201918 # number of demand (read+write) misses system.l2.demand_misses::cpu.itb.walker 34225 # number of demand (read+write) misses system.l2.demand_misses::cpu.inst 1937307 # number of demand (read+write) misses system.l2.demand_misses::cpu.data 11339422 # number of demand (read+write) misses system.l2.demand_misses::total 13512872 # number of demand (read+write) misses system.l2.overall_misses::cpu.dtb.walker 201918 # number of overall misses system.l2.overall_misses::cpu.itb.walker 34225 # number of overall misses system.l2.overall_misses::cpu.inst 1937307 # number of overall misses system.l2.overall_misses::cpu.data 11339422 # number of overall misses system.l2.overall_misses::total 13512872 # number of overall misses system.l2.ReadReq_accesses::cpu.dtb.walker 29905927 # number of ReadReq accesses(hits+misses) system.l2.ReadReq_accesses::cpu.itb.walker 1401493 # number of ReadReq accesses(hits+misses) system.l2.ReadReq_accesses::cpu.inst 11859895 # number of ReadReq accesses(hits+misses) system.l2.ReadReq_accesses::cpu.data 30523388 # number of ReadReq accesses(hits+misses) system.l2.ReadReq_accesses::total 73690703 # number of ReadReq accesses(hits+misses) system.l2.Writeback_accesses::writebacks 7828991 # number of Writeback accesses(hits+misses) system.l2.Writeback_accesses::total 7828991 # number of Writeback accesses(hits+misses) system.l2.UpgradeReq_accesses::cpu.data 49526 # number of UpgradeReq accesses(hits+misses) system.l2.UpgradeReq_accesses::total 49526 # number of UpgradeReq accesses(hits+misses) system.l2.ReadExReq_accesses::cpu.data 4523307 # number of ReadExReq accesses(hits+misses) system.l2.ReadExReq_accesses::total 4523307 # number of ReadExReq accesses(hits+misses) system.l2.demand_accesses::cpu.dtb.walker 29905927 # number of demand (read+write) accesses system.l2.demand_accesses::cpu.itb.walker 1401493 # number of demand (read+write) accesses system.l2.demand_accesses::cpu.inst 11859895 # number of demand (read+write) accesses system.l2.demand_accesses::cpu.data 35046695 # number of demand (read+write) accesses system.l2.demand_accesses::total 78214010 # number of demand (read+write) accesses system.l2.overall_accesses::cpu.dtb.walker 29905927 # number of overall (read+write) accesses system.l2.overall_accesses::cpu.itb.walker 1401493 # number of overall (read+write) accesses system.l2.overall_accesses::cpu.inst 11859895 # number of overall (read+write) accesses system.l2.overall_accesses::cpu.data 35046695 # number of overall (read+write) accesses system.l2.overall_accesses::total 78214010 # number of overall (read+write) accesses system.l2.ReadReq_miss_rate::cpu.dtb.walker 0.006752 # miss rate for ReadReq accesses system.l2.ReadReq_miss_rate::cpu.itb.walker 0.024420 # miss rate for ReadReq accesses system.l2.ReadReq_miss_rate::cpu.inst 0.163349 # miss rate for ReadReq accesses system.l2.ReadReq_miss_rate::cpu.data 0.274217 # miss rate for ReadReq accesses system.l2.ReadReq_miss_rate::total 0.143077 # miss rate for ReadReq accesses system.l2.UpgradeReq_miss_rate::cpu.data 0.976194 # miss rate for UpgradeReq accesses system.l2.UpgradeReq_miss_rate::total 0.976194 # miss rate for UpgradeReq accesses system.l2.ReadExReq_miss_rate::cpu.data 0.656467 # miss rate for ReadExReq accesses system.l2.ReadExReq_miss_rate::total 0.656467 # miss rate for ReadExReq accesses system.l2.demand_miss_rate::cpu.dtb.walker 0.006752 # miss rate for demand accesses system.l2.demand_miss_rate::cpu.itb.walker 0.024420 # miss rate for demand accesses system.l2.demand_miss_rate::cpu.inst 0.163349 # miss rate for demand accesses system.l2.demand_miss_rate::cpu.data 0.323552 # miss rate for demand accesses system.l2.demand_miss_rate::total 0.172768 # miss rate for demand accesses system.l2.overall_miss_rate::cpu.dtb.walker 0.006752 # miss rate for overall accesses system.l2.overall_miss_rate::cpu.itb.walker 0.024420 # miss rate for overall accesses system.l2.overall_miss_rate::cpu.inst 0.163349 # miss rate for overall accesses system.l2.overall_miss_rate::cpu.data 0.323552 # miss rate for overall accesses system.l2.overall_miss_rate::total 0.172768 # miss rate for overall accesses system.l2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2.blocked::no_mshrs 0 # number of cycles access was blocked system.l2.blocked::no_targets 0 # number of cycles access was blocked system.l2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2.fast_writes 0 # number of fast writes performed system.l2.cache_copies 0 # number of cache copies performed system.l2.writebacks::writebacks 3690717 # number of writebacks system.l2.writebacks::total 3690717 # number of writebacks system.l2.no_allocate_misses 0 # Number of misses that were no-allocate system.tol2bus.throughput 1203101281 # Throughput (bytes/s) system.tol2bus.data_through_bus 3751029976 # Total data (bytes) system.tol2bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iobus.throughput 55985226 # Throughput (bytes/s) system.iobus.data_through_bus 174550774 # Total data (bytes) _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
