Hi, I am using gem5 ARM with classic memory config and l2 tride prefetcher. There are 4 cores in the system and a shared l2. I think I may have hit a coherence protocol deadlock. Here's whats happening.
Cycle 0: Core 2: Schedules an UpgradeReq to be sent out at Cycle 2. Between Cycle 0 and Cycle 2 , there are a lot of L2 prefetch requests which blocks the L2 (they use up all the MSHR's). All prefetches are a hit in Core:2 and it has to respond to the PF_request. Cycle 2, Bus issues snoop request for UpgradeReq(from Core2) to all L1's. However, since l2_cpuside port is not part of the bus slave port list, the request is a normal request at L2 and not a snoop. Because of this (and since L2 is blocked now) the L2 schedules a retry and Core:2 packet queue waits for the retry, which the L2 will send only when it is unblocked. Since Core2: packet queue is the entity that has to unblock L2 by sending the prefetch response, there is a deadlock here(It is waiting for a retry). When I tried to limit the prefetch requests such that PF does not block the cache at all, there was no deadlock. However, the root of the problem is that L2 should respond to the UpgradeReq even when it is blocked just like the L1's do. I would be very grateful if a solution is suggested. Thanks Srini _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
