I have a related post on the mailing list about this, and I indicate a workaround to the problem. It's not ideal, but it works. Keep in mind, that just because you didn't modify the protocol, doesn't mean errors aren't bound to occur.
Malek On Sun, Apr 27, 2014 at 3:02 AM, sunlong <niang...@gmail.com> wrote: > Hi all, > > I am trying to modify MOESI_hammer protocol. First I add l3 cache. Second, > I add flush all cachelines by issuing FlushReq through Sequencer. > > I meet some problems when run some bench mark: > > 1. Tried to read unmapped address 0x40. > 2. fatal: Ruby functional read failed for address. > > I have search for fommer messages in gem5. And suppose that there may be > problems when state changes in L1CacheController and Directory Controller. > I don't really understand why there will be conflictions between > FunctionalAccess and TimingAccess. > > ps, I use SE.py,MOSEI_hammer protocol, timing simple CPU. > > There must be some cases I did not notice when modify the protocol. Can > any one give some advice on how to debug? > > Sunlong > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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