Hello, I've been working with the Mesh topology in Garnet and found the requirement for the number of directory controllers to be equal to the number of cores. However, I've been digging into the details of the directory controller unit and found that each one instantiates a memory controller. Does this notion basically simulate a separate memory channel to DRAM per directory controller? If so, it seems a bit odd to simulate 8 channels to main memory for an 8 core Mesh and 64 channels to main memory for a 64 core Mesh.
Thanks, Paco Sangaiah (Drexel University)
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