Re: [gem5-users] Change port range (To avoid collision)

[Andreas Hansson via gem5-users]

Hi Alberto,

Have a look at the address range for the interrupt controller in your Python 
config. The message suggests that the PIO port of the interrupt controller 
overlaps with “memory”, or at least something behind the L2 cache.

You can run with the BusAddrRanges debug flag for more information.

Good luck.

Andreas

From: Alberto Martinez via gem5-users 
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Reply-To: Alberto Martinez <alber...@gmail.com<mailto:alber...@gmail.com>>, 
gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Date: Monday, May 26, 2014 at 5:24 PM
To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Subject: [gem5-users] Change port range (To avoid collision)

Hello guys,
I am trying to run a Nehalem configuration (written by Mitch and Nithesh), but 
I got this error:

0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
fatal: system.tol2bus has two ports with same range:
system.cpu.interrupts.pio
system.l2.cpu_side

How can I modify the range of the ports being used? (I am not establishing the 
range anywhere, or at least, I think Im not)

The mem configuration in the script is done this way:

# Configure L2 cache
if config.has_section('l2'):
    l2_options = dict(config.items('l2'))
    if l2_options.has_key('prefetcher'):
        l2_options['prefetcher'] = eval(l2_options['prefetcher'])
#    system.l2 = BaseCache(clock = cpu.clock,

    system.l2 = BaseCache(**l2_options)
#    system.tol2bus = CoherentBus(clock = cpu.clock, width = 32)

    system.tol2bus = CoherentBus(width = 32)
    system.l2.cpu_side = system.tol2bus.master
    if config.has_section('l3') == False:
        system.l2.mem_side = system.membus.slave
    cpu.connectAllPorts(system.tol2bus)
else:
     cpu.connectAllPorts(system.membus)

# Configure L3 cache
if config.has_section('l3'):
    l3_options = dict(config.items('l3'))
    if l3_options.has_key('prefetcher'):
        l3_options['prefetcher'] = eval(l3_options['prefetcher'])
#    system.l3 = BaseCache(clock = cpu.clock,

    system.l3 = BaseCache(**l3_options)
#    system.tol3bus = CoherentBus(clock = cpu.clock, width = 16)

    system.tol3bus = CoherentBus(width = 16)
    system.l2.mem_side = system.tol3bus.slave
    system.l3.cpu_side = system.tol3bus.master
    system.l3.mem_side = system.membus.slave


You can find all scripts at Nithesh's site:
https://sites.google.com/site/nitheshkurella/scipts

Thanks a lot,
Alberto





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