Hi Ahmad,
You can tune the page policies of both. By default the DRAMCtrl model in gem5
uses an open-adaptive policy with FR-FCFS scheduling, which tends to be the
best possible when it comes to row hits. You can change this if you want, just
modify the page_policy parameter of the controller instance. The default in
DRAMSim2 is a simpler open-page policy with a limit of 4 access to the same
page before closing it. Thus, you are far more likely to get hit by the
opening/closing.
I hope that all makes sense.
Andreas
From: Ahmad Hassan via gem5-users
<[email protected]<mailto:[email protected]>>
Reply-To: Ahmad Hassan <[email protected]<mailto:[email protected]>>,
gem5 users mailing list <[email protected]<mailto:[email protected]>>
Date: Monday, 2 June 2014 15:04
To: gem5 users mailing list <[email protected]<mailto:[email protected]>>
Subject: Re: [gem5-users] DDR timing model
Hi Andreas,
Thanks for the details. But the same workload gives significant increase in
average memory access time if i run gem5 with integrated dramsim2 and increase
only tRCD and tRP. As you said, both tRCD and tRP are associated with opening
and closing of row. The results of dramsim2 and gem5 DDR3 memory model suggests
that gem5 keeps the rows open for much longer duration which causes
significantly higher pageHitRate.
Regards,
On 2 June 2014 10:36, Andreas Hansson
<[email protected]<mailto:[email protected]>> wrote:
Hi Ahmad,
Increasing tRCD and tRP will essentially make it more costly to open and close
a page. If you have good page hit-rate, and good distribution over the banks,
then the effects of the increased timings can be hidden (at least from the
perspective of the average latency). When you increase tCL you are delaying
every single access.
bytesPerActivate is a histogram statistic associated with the DRAM controller.
You should find it in the stats.txt along with all the other stats.
Andreas
From: Ahmad Hassan via gem5-users
<[email protected]<mailto:[email protected]>>
Reply-To: Ahmad Hassan <[email protected]<mailto:[email protected]>>,
gem5 users mailing list <[email protected]<mailto:[email protected]>>
Date: Monday, 2 June 2014 10:29
To: gem5 users mailing list <[email protected]<mailto:[email protected]>>
Subject: [gem5-users] DDR timing model
Hi Andreas,
[Moving discussion from http://reviews.gem5.org/r/2109]
If I only increase the tCL parameter from 13.75ns to 61ns [4.4x times default
DDR3), then I notice 3.2x times increase in avgMemAccLat. This is what we
should expect. Can we use tCL to simulate slow DDR3? My understanding is that,
we cannot do that because tCL represents column address strobe and it affects
bandwidth.
But I cannot produce the same result by changing tRCD = '61ns', tRP = '165ns'.
tRCD affects read latency and tRP affects write latency. I only get an increase
in avgMemAccLat by 1.2x times default DDR3.
Results:
For default DDR3:
avgMemAccLat 22133.24
totMemAccLat 12166996811
For tRCD = '61ns', tRP = '165ns'.
avgMemAccLat 27473.08
totMemAccLat 15104591550
For tCL = '61ns'
avgMemAccLat 71630.94
totMemAccLat 39376746052
I did not find any 'bytesPerActive' attribute in stats file. Where shall I see
this?
Thanks.
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